Using FORAY Models to Enable MPSoC Memory Optimizations
With the technology advances it becomes feasible to implement a large multiprocessor system on a single chip. In such System-on-Chips (SoCs), a significant portion of energy is spent in the memory subsystem. There are several approaches reducing this energy, including the ones at physical, architecture and algorithmic levels. Classical approaches, including algorithmic and some architectural approaches, use static analysis and transformation of the application source code. However, often it is not possible to perform static analysis and optimization of a program's memory access behavior unless the program is written in an easily analyzable form, e.g., free from pointer arithmetic.