Variation Aware Dynamic Power Management for Chip Multiprocessor Architectures

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Provided by: edaa
Topic: Hardware
Format: PDF
With the increasing levels of variability in the characteristics of VLSI circuits and continued uncertainty in the operating conditions of processors, achieving predictable power efficiency and high performance in the electronic systems has become a daunting, yet vital, task. This paper tackles the problem of system-level Dynamic Power Management (DPM) in the state-of-the-art Chip Multi-Processor (CMP) architectures that are manufactured in nanoscale CMOS technologies with large process variations or are operated under widely varying environmental conditions over their lifetime.
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