Provided by: University of California
Date Added: Dec 2012
In this paper, the authors present a variation-tolerant tasking technique for tightly-coupled shared memory processor clusters that relies upon modeling advance across the hardware/software interface. This is implemented as an extension to the OpenMP 3.0 tasking programming model. Using the notion of Task-Level Vulnerability (TLV) proposed here, they capture dynamic variations caused by circuit-level variability as high-level software knowledge. This is accomplished through a variation aware hardware/software codesign where: hardware features variability monitors in conjunction with online per-core characterization of TLV metadata; software supports a Task-level Errant Instruction Management (TEIM) technique to utilize TLV metadata in the runtime OpenMP task scheduler.