VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a micro architecture-aware model for process variation - including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of micro-architectural blocks as a function of clock frequency and the amount of variation.
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