Universitat Politecnica de Catalunya
Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper, the authors focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this paper, they propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, they implement 32-bit adders in the 90nm technology node for VCTA and compare them with implementations that make use of standard cells.