Institute of Research and Journals (IRAJ)
In this paper, an Advanced Microcontroller Bus Architecture (AMBA) compliant memory controller is designed for system memory control with the main memory consisting of SRAM, ROM and dual port cache. As microprocessor performance has improved in recent years, it has become increasingly important to provide a high-bandwidth, low-latency memory subsystem to achieve the full performance potential of these processors. Dual port caches have been used extensively to patch over this mismatch. The memory controller is the part of the system that, well, controls the memory.