Verilog Implementation of Reconfigurable Routers for Low Power

Provided by: Auricle Technologies
Topic: Hardware
Format: PDF
Network-on-Chip (NoC) designs are based on a compromise among latency, power dissipation or energy, and the balance is usually defined at design time. However, setting all parameters, such as buffer size, at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, e.g. a portable phone downloads a new service. Large buffer sizes can ensure performance during the execution of different applications, but unfortunately, these same buffers are mainly responsible for the router total power dissipation.

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