VERVE: A Framework for Variation-Aware Energy Efficient Synthesis of NoC-Based MPSoCs with Voltage Islands

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern Multi-Processor System-on-Chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial for designing energy-efficient systems. The authors note that by performing voltage island placement appropriately, the two major unintended consequences of variations on the circuit characteristics (altered delay and power dissipation) can be traded-off, in order to minimize overall system energy.

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