European Design and Automation Association
The authors address the problem of analyzing the performance of System-on-Chip (SoC) architectures in the presence of variations. Existing techniques such as gate-level statistical timing analysis compute the distributions of clock frequencies of SoC components. However, they demonstrate that translating component-level characteristics into a system-level performance distribution is a complex and challenging problem due to the inter-dependencies between components execution, indirect effects of shared resources, and interactions between multiple system-level \"Execution paths\". They argue that accurate variation aware system-level performance analysis requires repeated system execution, which is prohibitively slow when based on simulation.