VHDL Implementation of an Optimized 8-Point FFT Using Vedic Multiplier

Provided by: Creative Commons
Topic: Hardware
Format: PDF
A high speed Fast Fourier Transform (FFT) design by using three algorithms is presented in this paper. In algorithm one, 4-bit binary multiplier based technique are used in FFT. In this paper used 128 number of slice and 207 4-input LUT for virtex-2 device family. In algorithm two, 4-bit adder based multiplier are used in FFT. In this paper used number of slice and 4-input LUT less compare to algorithm one technique. In algorithm three, 4-bit Vedic multiplier based technique are used in FFT. In this paper used in three 4-bit ripple carry adder and four 22 Vedic multiplier.

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