VHDL Implementation of Floating Point Multiplier Using Vedic Mathematics
In this paper, the authors present a binary floating point multiplier based on Vedic algorithm. To improve power efficiency a new algorithm called Urdhva-Triyakbhyam has been implemented for 24x24 bit multiplier design. By using this approach number of components can be decreased and complexity of hardware circuit can be decrease. In this paper, Vedic multiplication technique is used to implement IEEE 754 floating point multiplier. The Urdhava-Triyakbhym sutra is used for the multiplication of Mantissa i.e., 24x24 bits.