VHDL Implementation of Scheduled Dataflow Architecture and the Impact of Efficient Way of Passing of Data
Since the invention of microprocessors around 1970, CPU performance improvement together with the Instruction Level Parallelism (ILP) had been the main focus of the computer industry. Currently, ILP seemed to have reached its limits, and together with the problem of power consumption and heat dissipation, there emerged the multi-core era. The focus had shifted from ILP to Thread Level Parallelism (TLP) and efficient use of multi-core processors. However, the detection of RAW (Read After Write) hazard technique relies on complex hardware in the current computers which may cause the designers to make the CPU consume a lot of energy and the design to be more complex.