VHDL Simulation of Reset Automatic Block, 64bit Latch Block, and Test Complete Blocks ForPD Detection Circuit System Using FPGA

Provided by: International Journal of Communications and Engineering
Topic: Hardware
Format: PDF
This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST)using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and B counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns.

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