Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Given the limited current understanding of the neural model of computation, hardware neural network architectures that impose a specific relationship between physical connectivity and model topology are likely to be overly restrictive. Here the authors introduce, in the SpiNNaker chip, an alternative approach: a mappable virtual topology using an asynchronous Network-on-Chip (NoC) that decouples the \"Logical\" connectivity map from the physical wiring. Borrowing the established digital RAM model for synapses, they develop a concurrent memory access channel optimized for neural processing that allows each processing node to perform its own synaptic updates as if the synapses were local to the node.
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