International Journal of Embedded and Software Computing (IJESC)
In the proposed paper, an approach has been carried out for the implementation of SEFDM transmitter on FPGA using Very High speed integrated circuit hardware Description Language (VHDL). A rigorous and efficient mathematical framework, to represent non-orthogonal signals using Inverse Discrete Fourier Transform (IDFT) blocks, is proposed. The standard IDFT operations can be efficiently realized with the Inverse Fast Fourier Transform (IFFT) algorithm. SEFDM systems propose bandwidth savings by multiplexing multiple non-orthogonal overlapping carriers. Xilinx 12.2 ISE software is used for optimization of the synthesizable VHDL code.