VLSI Architecture of Parallel Multiplier- Accumulator Based on Radix-2 Modified Booth Algorithm

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Provided by: Interscience Open Access Journals
Topic: Hardware
Format: PDF
A new architecture of Multiplier and ACcumulator (MAC) for high-speed arithmetic, by combining multiplication with accumulation and devising a hybrid type of Carry Save Adder (CSA), the performance was improved. Since, the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1's-complement-based radix-2 Modified Booth's Algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands.
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