VLSI Design and Implementation of Binary Number Multiplier Based on Urdhva Tiryagbhyam Sutra with Reduced Delay and Area
In this paper, the authors proposed the design of high speed and area efficient binary number multiplier often called binary Vedic multiplier using the techniques of ancient Indian Vedic Mathematics i.e. Urdhva Tiryagbhyam Sutra. Urdhva Tiryagbhyam Sutra is the Vedic method for multiplication which strikes a difference in the actual process of multiplication itself, giving minimum delay for multiplication of all types of numbers, either small or large. The paper has proved the efficiency of binary number multiplier designed using Urdhva Tiryagbhyam Sutra where multiplication process enables parallel generation of intermediate products and eliminates unwanted multiplication steps.
Provided by: International Research Publication House (IRPH) Topic: Hardware Date Added: Jul 2013 Format: PDF