International Journal of Electronics and Computer Science Engineering
In this paper the authors present Very Large Scale Integration (VLSI) design and simulation of a ternary logic gates and CMOS ternary SRAM cell. The simple ternary inverter, positive ternary inverter and negative ternary inverter are designed in 180nm technology. The ternary NAND gate and ternary NOR gate are also designed and simulated. The ternary SRAM consists of cross-coupled ternary inverters. SPICE simulations confirmed that the functional behavior of the read and write operations is correct.