VLSI Design and Performance Analysis of Different Full Adder Topologies at 0.25 Micrometer Technology Node
Full adders are the most important components in digital design which not only perform addition operations, but also helpful in calculating several other functions such as subtraction, multiplication and division operations. Different types of adders are frequently essential in VLSI technology according to the requirement in processors to ASICs. In modern research, the authors have found that Complementary Pass transistor Logic (CPL) is much more power-efficient than complementary CMOS. In this paper, they describe the power consumption and propagation delay of one-bit CMOS (Complementary Metal-Oxide Semiconductor) full adder, CPL full adder, domino logic full adder and transmission gate full adder designed using TANNER EDA, using 0.25 micrometer technology node with different CMOS logic design styles.