VLSI Implementation & Design of Complex Multiplier for FFT Using ASIC-VLSI

Provided by: Serials Publications
Topic: Hardware
Format: PDF
A 16-bit Radix 4 FFT requires a complex multiplier, adder and subtractor that can handle signed two's compliment. The implementation of a complex multiplier uses both the adders and subtractor needed for the FFT. The design of a FFT can be derived from the complex multiplier design. The goal of the device is to have it operate at 100MHz. The complex multiplier must work at 100MHz. Because the design is limited to 40 pins an 8-bit signed two's compliment complex multiplier is implemented. This implementation also contains an 8-bit complex adder and subtractor.

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