VLSI Implementation of Area Efficient Fast Parallel FIR Digital Filters Based on Fast FIR Algorithm

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Provided by: Iosrjournals
Topic: Hardware
Format: PDF
In this paper, the authors propose new parallel FIR (Finite Impulse Response) structures to reduce the hardware complexity of higher order FIR filter with symmetric co-efficient based on Fast FIR Algorithms (FFAs). The objective is to design an area-efficient fast parallel FIR filter structure which constraint that the filter taps must be a multiple of 2 or 3. In this paper, they discussed for three parallel FIR Filter implementation based on recursively using proposed 2 parallel FIR structure.
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