International Journal of Innovative Science and Modern Engineering (IJISME)
In this paper, the authors present an efficient architecture for the implementation of a delayed least mean square Adaptive filter. For achieving lower adaptation-delay and area-delay-power, they use a novel partial product generator and propose an optimized balanced pipelining across the time-consuming combinational blocks of the structure. From synthesis results, they find that the proposed design with less Area-Delay Product (ADP) and less Energy-Delay Product (EDP) than the best of the existing systolic structures, for various filter lengths. They propose an efficient fixed-point implementation scheme in the proposed architecture.