VLSI Implementation of DWT Using Systolic Array Architecture
In this paper, the authors present an implementation of Discrete Wavelet Transform (DWT) using Systolic architecture in VLSI. This architecture consists of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power.