VLSI Implementation of Huffman Decoder Using Binary Tree Algorithm
Compression is useful technique in digital system, as it reduces the channel bandwidths and storage size. This paper presents Huffman decoder based on new binary tree method for improving usage of memory and bandwidth. The proposed Huffman decoder is implemented by using ASIC and FPGA design methodologies. To implement the encoder and decoder architectures, 0.6 Micron standard cell library was used for ASIC implementation. Various performance metrics like leakage power, dynamic power, area and number of registers are obtained by using ASIC and FPGA implementations and the results are compared. The simulations are carried out by using Modelsim tool.