Wagging Logic: Implicit Parallelism Extraction Using Asynchronous Methodologies

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Provided by: The University of Maine at Machias
Topic: Hardware
Format: PDF
Asynchronous circuits have a number of potential performance advantages over their synchronous equivalents due to the ability to exploit average case performance. These advantages are off-set by the loss of performance caused by the handshaking overheads which causes designs to be throughput bound. This paper investigates the nature of the throughput problem and proposes a novel automatic approach to overcome its effect. The designs generated using the method not only cease suffering from a throughput bottleneck, but also attain the parallel computation properties despite their original sequential specification.
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