Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Provided by: Institute of Electrical & Electronic Engineers
Topic: Mobility
Format: PDF
Current commercial Systems-on-Chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The Network-on-Chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange.

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