Working with Process Variation Aware Caches

Provided by: edaa
Topic: Hardware
Format: PDF
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this paper, by considering on-chip data caches, the authors study the effect of access latency variations on performance. They discuss performance losses due to the worst-case design, wherein the entire cache operates with the worst-case process variation delay, followed by process variation aware cache designs which work at set-level granularity.

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