Association for Computing Machinery
The Power Delivery Network (PDN) is a major consumer of interconnect resources in deep-submicron designs (i.e., more than 30% of the entire routing area). Hence, efficient early-stage PDN optimization enables the designers to ensure a desired power-performance envelope. On the other hand as technology scales, gate delays become more sensitive to power supply variation. In addition, emerging 3D designs are more prone to supply voltage and temperature variation due to increased power density. In this paper, the authors develop accurate inverter cell delay and output slew models under supply voltage and temperature variation.