Institute of Electrical & Electronic Engineers
Voltage scaling is desirable in Static RAM (SRAM) to reduce energy consumption. However, commercial SRAM is susceptible to functional failures when VDD is scaled down. Although several published SRAM designs scale VDD to 200 - 300 mV, these designs do not sufficiently consider SRAM robustness, limiting them to small arrays because of yield constraints, and may not correctly target the minimum energy operation point. The authors examine the effects on area and energy for the differential 6T and 8T bit cells as VDD is scaled down, and the bit cells are either sized and doped, or assisted appropriately to maintain the same yield as with full VDD. SRAM robustness is calculated using importance sampling, resulting in a seven-order run-time improvement over Monte Carlo sampling.