Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges

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Provided by: The China Press Berhad
Topic: Hardware
Format: PDF
Three-Dimensional (3D) Integrated Circuits (ICs) that stack multiple dies vertically using Through-Silicon Vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the \"Known good die\" problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield.
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