Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor

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Provided by: edaa
Topic: Hardware
Format: PDF
Network-on-Chip (NoC) is a promising solution for efficient interconnection between processor cores in Chip-Multi-Processor (CMP). This paper is focusing on the energy-efficient design of buffers, a group of the most important components in NoC. From the authors' investigation, an overwhelming majority of \"Zero\" is contained in the packets transmitting in NoC for CMP. A zero-efficient buffer design is proposed as well as the error control scheme. Compared with conventional design, up to 43% energy consumption can be saved.
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