The accessing of both DIMMs at the same time is what makes it critical for both DIMMs to be VERY closely matched.
Any difference in CAS latency, speed, even the length of the traces on the DIMM circuit board can result in timing discrepancies between 2 DIMMs from different manufacturing lots let alone 2 different suppliers.
Even different manufacturing lots of the same memory ICs can have timing differences.
Anything that results in a timing difference between the 2 DIMMs in a dual channel configuration will cause system stability problems, if not data errors.
Look at it this way, at 2 MPH, you have a lot of time to match the speed of 2 different cars over a 100 foot race.
At 150 MPH, both cars need to be running exactly the same to enter and exit a 100 foot timing gap at the same time.
Chas