counter design in vhdl

my counter(updown) design specifications:
counter should have startvalue,stopvalue,stepsize,updown,trigger and reset as the inputs apart from clk, and the output is countervalue.
when reset=1 the counter should assigned to zero, during the posedge of the clock and trigger=1 then the startvalue should be assigned to intermediate signal let us say signal1.when trigger=0 and depending on the updown value it should count up or down.moreover the counter should stop when it will reach the maximum value i.e.stopvalue. and i don’t want to count again after reaching the maximum value it should be assigned to zero only that means i wants to count only once from starting value to maximum value.make sure that overflw,underflow should not happen.