A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage

A novel fast locking Digital Phase-Locked Loop (DPLL) has been proposed with simple control unit to improve locking time. A Frequency Difference Stage (FDS) is added to produce a 3-bit code represents the difference between the input frequency and the output frequency of the PLL. This code is used to control a Programmable Charge Pump (PCP) output current. As the difference between the two frequencies decreases, the PCP output current decreases to obtain smooth PLL locking. As locking is achieved, the PCP operates with its conventional current.