A Modified Power Gating Technique for Ground Bounce Noise Reduction in CMOS Adder Circuit

As technology is continuously scaling down, leakage current is increasing exponentially. Power gating is a very effective technique to reduce the leakage current and leakage power by using sleep transistors to turn off the functional blocks when they are not in use. But when circuit transition goes from sleep to active mode, abrupt transitions introduces ground bounce noise in the circuit which disturbs the normal working of any circuit and tends to give wrong output and also reduces the reliability of circuit.