Design and Simulation of 8255 Programmable Peripheral Interface Adapter Using VHDL

The 8255A Programmable Peripheral Interface (PPI) implements a general-purpose I/O interface to connect peripheral equipment to a microcomputer system bus. The core’s functional configuration is designed by VHDL code and designed input signal (test bench) for PPI 8255, which is generated by VHDL code. Simulated result is verified for three 8-bit peripheral ports – ports A, B, and C, three programming modes for peripheral ports: mode 0 (basic input/output), mode 1 (strobed input/ output), and mode 2 (bidirectional), total of 24 programmable I/O lines.