Electromigration Modeling and Full-Chip Reliability Analysis for BEOL Interconnect in TSV-Based 3D ICs

Electro-Migration (EM) is a critical problem for interconnect reliability of modern Integrated Circuits (ICs), especially as the feature size becomes smaller. In Three-Dimensional (3D) IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, Through-Silicon-Vias (TSVs) and landing pads. Meanwhile, the thermo-mechanical stress due to the TSV can also cause reduction in the failure time of wires. However, there is very little study on EM issues that consider TSVs in 3D ICs.