FPGA Based High-Speed A-OMS LUT & FIR System Design

A-OMS LUT design is an advanced approach for optimizing the size of a LUT required for the direct storage of complex computational values. It is known that in FPGAs the DSP blocks plays a major role for improved performance that consist of the multiply and accumulate structures that are replaced with conventional LUT-based multiplier. So far, many algorithms have been implemented for optimizing Look-up-tables of DSP cores in FPGAs. In this paper, a new method “A-OMS LUT” is presented to provide better performance than the previously specified methods.