A High Speed Binary Floating Point Multiplier Using Vedic Algorithm
Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point single precision multiplier is implemented in HDL. This paper presents a high speed binary single precession floating point multiplier based on Vedic algorithm. To improve speed multiplication of mantissa is done using Vedic multiplier replacing carry save multiplier. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions.
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