Addition is the most complex operation in a floating-point unit and can cause major delay while requiring a significant area. Over the years, the VLSI community has developed many floating-point adder algorithms aimed primarily at reducing the overall latency. An efficient design of the floating-point adder offers major area and performance improvements for FPGAs. This paper studies the implementation of standard; Leading-One Predictor (LOP); and far and close data path (2-path) floating-point addition algorithms in FPGAs.