In this paper, an efficient technique for implementation of soft-error tolerant shift registers is presented. The proposed paper uses two implementations of the basic registers with different structures operating in parallel. A soft-error occurring in either shift registers causes the outputs of the shift registers to differ, or mismatch, for at least one sample. The shift registers are specifically designed so that, when a soft error occurs, they produce distinct error patterns at the shift registers output. An error detection circuit monitors the basic shift registers outputs and identifies any mismatches.