In this paper, the authors propose a novel design of full subtractor. The design is intended to minimize leakage power and circuit area. Proposed full subtractor is designed by using three transistor XOR gate to generate difference and a Differential Cascade Voltage Switch Logic (DCVSL) multiplexer to generate borrow. The design technique ensures lesser circuit area and lesser power dissipation in nano-scale Very Large Scale Integration (VLSI) systems for a wide range of power supply voltages. Simulations were carried out by using Tanner EDA tool, DSCH2, Microwind and LTSpice at 35nm technology.