BCD Adder and Multiplier Using Reversible Logic Design

Filters are widely used in the world of communication and computation. To design a Finite Impulse Response (FIR) filter that satisfies all the required conditions is a challenge. Power consumption by the multiplier and adder blocks in the architecture is the prime cause for concern in FIR design. In this paper, design of an FIR filter entirely using Reversible logic is presented. Reversible logic is emerging as a promising computing paradigm having widespread areas of application. It is based on the fundamental that zero energy dissipation would be achieved if the design is made of reversible gates.

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