Behavioural Modelling and Simulation of PLL Based Integer N Frequency Synthesizer using Simulink

Behavioral modeling and simulation of a PLL based integer n frequency synthesizer has been illustrated in this paper. The synthesizer generates a signal of 5.15-5.25GHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the PLL building blocks are modeled and simulated using Simulink. The PLL performance has been evaluated using Matlab. It is verified that the PLL loop bandwidth and phase margin are 0.25MHz and 69.125 degree respectively, which satisfies the correct transfer function.

Subscribe to the Innovation Insider Newsletter

Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays

Subscribe to the Innovation Insider Newsletter

Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays

Resource Details

Provided by:
International Research Publication House
Topic:
Hardware
Format:
PDF