Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Nano-Technology

Power and delay optimization is a very crucial issue in low voltage applications. In this paper, the authors present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design. By using this approach full adder is being designed using 12 transistors. They can reduce the value of total power dissipation by applying the AVLG (Adaptive Voltage Level at Ground) technology in which the ground potential is raised and AVLS (Adaptive Voltage Level at Supply) in which supply potential is increased.

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