Design and Analysis of a 32 Bit Linear Feedback Shift Register Using VHDL
In this paper, the authors propose a 32 bit linear feedback shift register which generates pseudo-random test patterns as the input bit is a linear function of its previous state. The total number of random state generated on LFSR depends on the feedback polynomial. As it is simple counter so it can count maximum of 2n -1 by using maximum feedback polynomial. Here in this paper, they implemented 32-bit LFSR on FPGA by using VHDL to study the performance and analysis the behavior of randomness.
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