Design and Implementation of 16-Bit Magnitude Comparator Using Efficient Low Power High Performance Full Adders

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Provided by: International Journal of Engineering Research and Applications (IJERA)
Topic: Hardware
Format: PDF
In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The paper attempts to examine the features of certain adder circuits which promise superior performance compared to existing circuits. The advantages of these circuits are low-power consumption, a high degree of regularity and simplicity. In this paper, the design of a 16-bit comparator is proposed. Magnitude comparison is one of the basic functions used for sorting in microprocessor and digital signal processing, so a high performance effective magnitude comparator is required.
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