Design and Implementation of a Two-Bit Binary Comparator Using Reversible Logic
Modern digital circuit designing is now focusing on the reversible circuits. It aims towards the designing of low power loss circuits in the area of nanotechnology, quantum computing, optical computing, signal processing etc. This paper presents an optimized two-bit binary comparator based on reversible logic using Feynman, Toffoli, TR, URG and BJN gates. Optimization of the comparator circuit is achieved on the basis of total number of gates used in the circuit and total number of garbage outputs generated.