Design and Implementation of a Two-Bit Binary Comparator Using Reversible Logic

Modern digital circuit designing is now focusing on the reversible circuits. It aims towards the designing of low power loss circuits in the area of nanotechnology, quantum computing, optical computing, signal processing etc. This paper presents an optimized two-bit binary comparator based on reversible logic using Feynman, Toffoli, TR, URG and BJN gates. Optimization of the comparator circuit is achieved on the basis of total number of gates used in the circuit and total number of garbage outputs generated.

Subscribe to the Innovation Insider Newsletter

Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays

Subscribe to the Innovation Insider Newsletter

Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays

Resource Details

Provided by:
International Journal of Scientific and Research Publication (IJSRP)
Topic:
Hardware
Format:
PDF