Design and Implementation of DA-Based Reconfigurable FIR Digital Filter Using FPGA Technology for Wireless Sensor Network
In this paper, the authors present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay power-efficient implementation of Finite Impulse Response (FIR) filter by systolic decomposition of Distributed Arithmetic (DA) based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the Look-Up Tables (LUTs) for DA-based computation to decide on suitable area-time trade-off. It is observed that by using smaller address-lengths for DA-based computing units, it is possible to reduce the memory-size but on the other hand that leads to increase of adder complexity and the latency.
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