Design and Testing of Prefix Adder for High Speed Application by Using Verilog HDL
Parallel prefix adder is the most flexible and widely used for binary addition. Parallel prefix adders are best suited for VLSI implementation. Numbers of parallel prefix adder structures have been proposed over the past years intended to optimize area, fan-out, and logic depth and inter connect count. This paper presents a new approach to redesign the basic operators used in parallel prefix architectures. The number of multiplexers contained in each Slice of an FPGA is considered here for the redesign of the basic operators used in parallel prefix tree.